Low power is the prime requirement to design power efficient VLSI circuits for portable electronic system. This paper presents a two modified approximate adder at 45nm technology. Performance of proposed adder is evaluated in terms of power dissipation, power delay product and compared with conventional full adder design. All the simulations are carried out using 45nm technology at 1.1v supply voltage at 500MHzas well as 1 GHz frequency. It can be seen from the results that leakage power reduces 71% for 1-bit approximate adder and energy consumption reduces upto82% while having dynamic power dissipation in acceptable range with marginal increase in delay.